1. Field of the Invention
The present invention relates to electronic packages, and more particularly, to an electronic package, a fabrication method thereof and a substrate structure for saving the fabrication cost.
2. Description of Related Art
Along with the rapid development of electronic industries, electronic products are developed toward the trend of multi-function and high performance. Accordingly, there have been developed various types of flip-chip packaging modules such as chip scale packages (CSPs), direct chip attached (DCA) packages and multi-chip modules (MCM), and 3D IC chip stacking technologies.
FIGS. 1A to 1F are schematic cross-sectional views showing a method for fabricating a 3D chip stacking-type electronic package 1 according to the prior art.
Referring to FIG. 1A, a silicon substrate 10 having a chip mounting side 10a and an opposite external connection side 10b is provided, and a plurality of via holes 100 are formed on the chip mounting side 10a of the silicon substrate 10.
Referring to FIG. 1B, an insulating material 102 and a conductive material such as copper are filled in the via holes 100 to form a plurality of through silicon vias (TSVs) 101. Then an RDL (Redistribution Layer) structure is formed on the chip mounting side 10a of the silicon substrate 10 and electrically connected to the TSVs 101.
In particular, to form the RDL structure, a dielectric layer 11 is first formed on the chip mounting side 10a of the silicon substrate 10. Then, a circuit layer 12 is formed on the dielectric layer 11 and has a plurality of conductive vias 120 formed in the dielectric layer 11 and electrically connected to the TSVs 101. Thereafter, an insulating layer 13 is formed on the dielectric layer 11 and the circuit layer 12, and portions of the circuit layer 12 are exposed form the insulating layer 13. Finally, a plurality of first conductive elements 14 such as solder bumps are formed on the exposed portions of the circuit layer 12.
Referring to FIG. 1C, a temporary carrier 40 (for example, a glass carrier) is attached to the insulating layer 13 through an adhesive 400. Then, the silicon substrate 10 is partially removed by grinding the external connection side 10b of the silicon substrate 10, thus forming an external connection side 10b′ exposing one end surfaces of the TSVs 101.
In particular, before the grinding process, the thickness h of the silicon substrate 10 (shown in FIG. 1B) is between 700 and 750 um. After the grinding process, the thickness h′ of the silicon substrate 10 (shown in FIG. 1C) is 100 um. Generally, the silicon substrate 10 is mechanically ground to a thickness of 102 to 105 um first and then ground by CMP (Chemical Mechanical Polishing) to 100 um.
The thickness t of the adhesive 400 is 50 um and limited by the total thickness variation (TTV) of the adhesive 400. Referring to FIG. 1C′, if the total thickness variation of the adhesive 400 is too large (about 10 um), the silicon substrate 10 tilts to one side. As such, the silicon substrate 10 easily cracks during the grinding process. Further, after the grinding process, only a portion of the TSVs 101 are exposed.
Furthermore, limited by the thickness h′ of the silicon substrate 10, the TSVs 101 are required to have a certain depth d (about 100 um). Therefore, the depth to width ratio of the TSVs 101 is limited to 100 um/10 um. That is, the depth d of the TSVs 101 is 100 um and the width w of the TSVs 101 is 10 um.
In addition, the TSVs 101 having a depth of only 10 um cannot be mass produced due to a high fabrication cost. In particular, since the total thickness variation of the adhesive 400 is about 10 um, the silicon substrate 10 can only be ground (including mechanical grinding and CMP) to a thickness h′ of 100 um. Subsequently, a wet etching process is required to remove the silicon substrate 10 by a thickness h″ of 90 um so as to expose the TSVs 101. However, the wet etching process is time-consuming and needs a large amount of etching solution, thus increasing the fabrication cost.
Referring to FIG. 1D, an insulating layer 15 is formed on the external connection side 10b′ of the silicon substrate 10 and the end surfaces of the TSVs 101 are exposed from the insulating layer 15. Then, a plurality of second conductive elements 16 are formed on and electrically connected to the end surfaces of the TSVs 101. The second conductive elements 16 can include a solder material or can be copper bumps. Further, the second conductive elements 16 can selectively include a UBM (Under Bump Metallurgy) layer 160.
Referring to FIG. 1E, a singulation process is performed along cutting paths S of FIG. 1D to obtain a plurality of silicon interposers 1a. Then, such a silicon interposer 1a is disposed on a packaging substrate 19 through the second conductive elements 16. The packaging substrate 19 has a plurality of conductive pads 190 electrically connected to the TSVs 101 through the second conductive elements 16. Further, an underfill 191 is formed between the silicon interposer 1a and the packaging substrate 19 to encapsulate the second conductive elements 16. The conductive pads 190 have a large pitch therebetween.
Referring to FIG. 1F, a plurality of electronic elements 17 such as chips are disposed on the first conductive elements 14 so as to be electrically connected to the circuit layer 12. In particular, the electronic element 17 is flip-chip bonded to the first conductive elements 14, and an underfill 171 is formed between the electronic elements 17 and the silicon interposer 1a to encapsulate the first conductive elements 14. The electronic elements 17 have a plurality of electrode pads having a small pitch therebetween.
Then, an encapsulant 18 is formed on the packaging substrate 19 to encapsulate the electronic elements 17 and the silicon interposer 1a. 
Finally, a plurality of solder balls 192 are formed on a lower side of the packaging substrate 19 for mounting an electronic device, for example, a circuit board (not shown). As such, an electronic package 1 is obtained.
In the electronic package 1, the silicon interposer 1a serves as a signal transmission medium between the electronic elements 17 and the packaging substrate 19. To achieve a suitable silicon interposer 1a, the TSVs 101 must be controlled to have a certain depth to width ratio (100 um/10 um), thus consuming a large amount of time and chemical agent and incurring a high fabrication cost.
Further, during the CMP process, copper ions of the TSVs 101 can diffuse into the silicon substrate 10 and cause bridging or leakage problems between the TSVs 101.
Therefore, how to overcome the above-described drawbacks has become critical.